View TC55NEM216ASTV55_3178532.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TC55NEM216ASTV55,70 2002-10-30 1/12 tentative toshiba mos digital integrat ed circuit silicon gate cmos 262,144-word by 16-bit full cmos static ram description the tc55nem216astv is a 4,194,304-bit static random access memory (sram) organized as 262,144 words by 16 bits. fabricated using toshiba's cmos silicon gate process technology, this de vice operates from a single 2.7 to 5.5 v power supply. advanced circuit technology provides bo th high speed and low power at an operating current of 3 ma/mhz (typ) and a minimum cycle time of 55 ns. it is automatically placed in low-power mode at 1 a standby current (typ) when chip enable ( ce ) is asserted high or chip select (cs) is asserted low. there are three control inputs. ce is used to select the device and for data retention control, and output enable ( oe ) provides fast memory access. data byte control pin ( lb , ub ) provides lower and upper byte access. this device is well suited to various microprocessor system applicat ions where high speed, low power an d battery backup are required. and, with a guaranteed operating extreme temperature range of ? 40 to 85c, the tc55nem216astv can be used in environments exhibiting extreme temperature conditio ns. the tc55nem216astv is available in a plastic 44-pin thin-small-outline package (tsop). features ? low-power dissipation operating: 15 mw/mhz (typical) ? single power supply voltage of 2.7 to 5.5 v ? power down features using ce ? data retention supply voltage of 2.0 to 5.5 v ? direct ttl compatibility for all inputs and outputs ? wide operating temperature range of ? 40 to 85c ? standby current (maximum): 20 a pin assignment (top view) 44 pin tsop pin names a0~a17 address inputs ce chip enable cs chip select r/w read/write control oe output enable lb , ub data byte control i/o1~i/o16 data inputs/outputs v dd power gnd ground nc no connection ? access times (maximum): tc55nem216astv 55 70 access time 55 ns 70 ns ce access time 55 ns 70 ns oe access time 30 ns 35 ns ? package: tsop ii44-p-400-0.80 (weight: g typ) a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 i/o4 v dd gnd i/o5 i/o6 i/o7 i/o8 r/w a15 a14 a13 a12 a16 a5 a6 a7 i/o16 i/o15 i/o14 i/o13 gnd v dd i/o12 i/o11 i/o10 i/o9 cs a8 a9 a10 a11 a17 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 oe ub lb ce
TC55NEM216ASTV55,70 2002-10-30 2/12 block diagram v dd gnd i/o1 i/o8 ce i/o9 i/o16 a0 a1 a2 a3 a4 a5 a16 ce a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a17 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 row address decoder row address buffer row address register memory cell array 2,048 128 16 (4,194,304) data input buffer data input buffer data output buffer data output buffer sense amp column address register column address decoder column address buffer clock generator ce r/w oe ub lb ce cs
TC55NEM216ASTV55,70 2002-10-30 3/12 operating mode mode ce cs oe r/w lb ub i/o1~i/o8 i/o9~i/o16 power l h l h l l output output i ddo l h l h h l high-z output i ddo read l h l h l h output high-z i ddo l h * l l l input input i ddo l h * l h l high-z input i ddo write l h * l l h input high-z i ddo l h h h l l high-z high-z i ddo l h h h h l high-z high-z i ddo output deselect l h h h l h high-z high-z i ddo cs standby * l * * * * high-z high-z i dds h * * * * * high-z high-z i dds standby * * * * h h high-z high-z i dds * = don't care h = logic high l = logic low maximum ratings symbol rating value unit v dd power supply voltage ? 0.3~7.0 v v in input voltage ? 0.3 * ~7.0 v v i/o input/output voltage ? 0.5~v dd + 0.5 v p d power dissipation 0.6 w t solder soldering temperature (10s) 260 c t stg storage temperature ? 55~150 c t opr operating temperature ? 40~85 c * : ? 2.0 v when measured at a pulse width of 20ns dc recommended operating conditions (ta = ? 40 to 85c) 5 v 10% 2.7 v~5.5 v symbol parameter min typ max min typ max unit v dd power supply voltage 4.5 5.0 5.5 2.7 5.0 5.5 v v ih input high voltage 2.2 ? v dd + 0.3 v dd ? 0.2 ? v dd + 0.3 v v il input low voltage ? 0.3 * ? 0.6 ? 0.3 * ? 0.2 v v dh data retention supply voltage 2.0 ? 5.5 2.0 ? 5.5 v *: ? 2.0v when measured at a pulse width of 20 ns
TC55NEM216ASTV55,70 2002-10-30 4/12 dc characteristics (ta = ? 40 to 85c, v dd = 5 v 10%) symbol parameter test condition min typ max unit i il input leakage current v in = 0 v~v dd ? ? 1.0 a i oh output high current v oh = 2.4 v ? 1.0 ? ? ma i ol output low current v ol = 0.4 v 2.1 ? ? ma i lo output leakage current ce = v ih or cs = v il or lb = ub = v ih or r/w = v il or oe = v ih , v out = 0 v~v dd ? ? 1.0 a min ? ? 35 l ddo1 ce = v il and cs = v ih and r/w = v ih , lb = ub = v il , i out = 0 ma, other input = v ih /v il t cycle 1 s ? 8 ? ma min ? ? 30 l ddo2 operating current ce = 0.2 v and cs = v dd ? 0.2 v and r/w = v dd ? 0.2 v, lb = ub = 0.2 v, i out = 0 ma, other input = v dd ? 0.2 v/0.2 v t cycle 1 s ? 3 ? ma i dds1 1) ce = v ih 2) cs = v il 3) lb = ub = v ih ? ? 3 ma ta = 25c ? 1 ? ta = ? 40~40c ? ? 3 i dds2 standby current 1) ce = v dd ? 0.2 v 2) cs = 0.2 v 3) lb = ub = v dd ? 0.2 v, ce = 0.2 v, cs = v dd ? 0.2 v ta = ? 40~85c ? ? 20 a dc characteristics (ta = ? 40 to 85c, v dd = 3 v 10%) symbol parameter test condition min typ max unit i il input leakage current v in = 0 v~v dd ? ? 1.0 a i oh output high current v oh = v dd ? 0.2 v ? 0.1 ? ? ma i ol output low current v ol = 0.2 v 0.1 ? ? ma i lo output leakage current ce = v ih or cs = v il or lb = ub = v ih or r/w = v il or oe = v ih , v out = 0 v~v dd ? ? 1.0 a min ? ? 30 i ddo2 operating current ce = 0.2 v and cs = v dd ? 0.2 v and r/w = v dd ? 0.2 v, lb = ub = 0.2 v, i out = 0 ma, other input = v dd ? 0.2 v/0.2 v t cycle 1 s ? 3 ? ma ta = 25c ? 1 ? ta = ? 40~40c ? ? 3 i dds2 standby current 1) ce = v dd ? 0.2 v 2) cs = 0.2 v 3) lb = ub = v dd ? 0.2 v, ce = 0.2 v, cs = v dd ? 0.2 v ta = ? 40~85c ? ? 20 a capacitance (ta = 25c, f = 1 mhz) symbol parameter test condition max unit c in input capacitance v in = gnd 10 pf c out output capacitance v out = gnd 10 pf note: this parameter is periodically sampled and is not 100% tested.
TC55NEM216ASTV55,70 2002-10-30 5/12 ac characteristics and operating conditions (ta = ? 40 to 85c, v dd = 5 v 10%) read cycle tc55nem216astv 55 70 symbol parameter min max min max unit t rc read cycle time 55 ? 70 ? t acc address access time ? 55 ? 70 t co chip enable access time ? 55 ? 70 t oe output enable access time ? 30 ? 35 t ba data byte control access time ? 55 ? 70 t coe chip enable low to output active 5 ? 5 ? t oee output enable low to output active 0 ? 0 ? t be data byte control low to output active 5 ? 5 ? t od chip enable high to output high-z ? 25 ? 30 t odo output enable high to output high-z ? 25 ? 30 t bd data byte control high to output high-z ? 25 ? 30 t oh output data hold time 10 ? 10 ? ns write cycle tc55nem216astv 55 70 symbol parameter min max min max unit t wc write cycle time 55 ? 70 ? t wp write pulse width 40 ? 50 ? t cw chip enable to end of write 45 ? 55 ? t bw data byte control to end of write 45 ? 55 ? t as address setup time 0 ? 0 ? t wr write recovery time 0 ? 0 ? t odw r/w low to output high-z ? 25 ? 30 t oew r/w high to output active 0 ? 0 ? t ds data setup time 25 ? 30 ? t dh data hold time 0 ? 0 ? ns note: t od , t odo , t bd and t odw are specified in time when an output becomes high impedance, and are not judged depending on an output voltage level. ac test conditions parameter test condition input pulse level 0.4 v, 2.4 v t r , t f 5 ns timing measurements 1.5 v reference level 1.5 v output load 100 pf + 1 ttl gate
TC55NEM216ASTV55,70 2002-10-30 6/12 ac characteristics and operating conditions (ta = ? 40 to 85c, v dd = 2.7 to 5.5 v) read cycle tc55nem216astv 55 70 symbol parameter min max min max unit t rc read cycle time 70 ? 85 ? t acc address access time ? 70 ? 85 t co chip enable access time ? 70 ? 85 t oe output enable access time ? 35 ? 45 t ba data byte control access time ? 70 ? 85 t coe chip enable low to output active 5 ? 5 ? t oee output enable low to output active 0 ? 0 ? t be data byte control low to output active 5 ? 5 ? t od chip enable high to output high-z ? 30 ? 35 t odo output enable high to output high-z ? 30 ? 35 t bd data byte control high to output high-z ? 30 ? 35 t oh output data hold time 10 ? 10 ? ns write cycle tc55nem216astv 55 70 symbol parameter min max min max unit t wc write cycle time 70 ? 85 ? t wp write pulse width 50 ? 55 ? t cw chip enable to end of write 55 ? 60 ? t bw data byte control to end of write 55 ? 60 ? t as address setup time 0 ? 0 ? t wr write recovery time 0 ? 0 ? t odw r/w low to output high-z ? 30 ? 35 t oew r/w high to output active 0 ? 0 ? t ds data setup time 30 ? 35 ? t dh data hold time 0 ? 0 ? ns note: t od , t odo , t bd and t odw are specified in time when an output becomes high impedance, and are not judged depending on an output voltage level. ac test conditions parameter test condition input pulse level 0.2 v, v dd ? 0.2 v t r , t f 5 ns timing measurements 1.5 v reference level 1.5 v output load 100 pf (include jig)
TC55NEM216ASTV55,70 2002-10-30 7/12 timing diagrams read cycle (see note 1) write cycle 1 (r/w controlled) (see note 4) ce t rc t acc t od valid data out t oe t be t bd hi-z hi-z t co oe t ba t coe t oh t odo t oee ub , lb address a0~a17 d out i/o1~16 cs r/w t as t wr valid data in t odw t wp t ds t dh t oew hi-z t cw t wc t bw ub , lb (see note 3) (see note 2) (see note 5) (see note 5) address a0~a17 d out i/o1~16 d in i/o1~16 ce cs
TC55NEM216ASTV55,70 2002-10-30 8/12 write cycle 2 ( controlled) (see note 4) write cycle 3 ( , controlled) (see note 4) ce ub lb r/w t wc t as t wr t wp t cw valid data in t ds t dh t be hi-z hi-z t odw t bw t coe ub , lb (see note 5) address a0~a17 d out i/o1~16 d in i/o1~16 ce cs r/w t wc t as t wr t wp valid data in t ds t dh hi-z hi-z t bw t be t coe t odw ub , lb t cw (see note 5) address a0~a17 d out i/o1~16 d in i/o1~16 ce cs
TC55NEM216ASTV55,70 2002-10-30 9/12 note: (1) r/w remains high for the read cycle. (2) if ce (or ub or lb ) goes low(or cs goes high) coincident with or after r/w g oes low, the outputs will remain at high impedance. (3) if ce (or ub or lb ) goes high(or cs goes low) coincide nt with or before r/w goes high, the outputs will remain at high impedance. (4) if oe is high during the write cycle, the outputs will remain at high impedance. (5) because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. data retention characteristics ( ta = ? 40 to 85c ) symbol parameter min typ max unit v dh data retention supply voltage 2.0 ? 5.5 v ta = ? 40~40c ? ? 3 i dds2 standby current ta = ? 40~85c ? ? 20 a t cdr chip deselect to data retention mode time 0 ? ? ns t r recovery time 5 ? ? ms controlled data retention mode cs controlled data retention mode (see note 2) ce v dd 4.5 v gnd v ih data retention mode t r (see note 1) (see note 1) t cdr v dd v dd ? 0.2 v ce v dd 4.5 v gnd v il data retention mode t r t cdr 0.2 v v ih cs v dd
TC55NEM216ASTV55,70 2002-10-30 10/12 , controlled data retention mode (see note 3) note: (1) in ce controlled data retention mode, minimum standby current mode is entered when cs 0.2 v or cs v dd ? 0.2 v. (2) when ce is operating at the v ih (min.) level(2.2 v), the operating current is given by i dds1 during the transition of v dd from 4.5 to 2.4 v. (3) in cs controlled data retention mode, minimum standby current mode is entered when cs 0.2 v. (4) in ub (or lb ) controlled data retention mode, minimum standby current mode is entered when ce ,cs 0.2 v or ce ,cs v dd ? 0.2 v. (5) when ub (or lb ) is operating at the v ih (min.) level(2.2 v), the oper ating current is given by i dds1 during the transition of v dd from 4.5 to 2.4 v. ub lb v dd 4.5 v gnd v ih data retention mode t r (see note 4) (see note 4) t cdr v dd v dd ? 0.2 v ub , lb
TC55NEM216ASTV55,70 2002-10-30 11/12 package dimensions weight: g (typ)
TC55NEM216ASTV55,70 2002-10-30 12/12 ? toshiba is continually working to improve the quality an d reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inhe rent electrical sensitivity and vulnerability to physical stress. it is the responsibility of t he buyer, when utilizing toshiba products , to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within s pecified operating ranges as set forth in the most recent toshi ba products specifications. also, pl ease keep in mind the precautions and conditions set forth in the ?handling guide for semicond uctor devices,? or ?toshiba semiconductor reliability handbook? etc.. ? the toshiba products listed in this document are inte nded for usage in general electronics applications (computer, personal equipment, office equipment, measuri ng equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunc tion or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control in struments, airplane or spaceship instruments, transportation instruments, traffic signa l instruments, combusti on control instruments, medical instruments, all types of safety devices, et c.. unintended usage of toshiba products listed in this document shall be made at th e customer?s own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intelle ctual property or other rights of the third parties which may re sult from its use. no license is grant ed by implication or otherwise under any intellectual property or other right s of toshiba corporation or others. ? the information contained herein is subject to change without notice. 000707eba restrictions on product use

▲Up To Search▲

Price & Availability of TC55NEM216ASTV55

	To Download TC55NEM216ASTV55 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .